1. Field of the Invention
The present invention relates generally to capacitors formed within integrated circuits. More particularly, the present invention relates to a double layer polysilicon capacitor formed within a shallow trench for use within integrated circuits.
2. Description of Related Art
Integrated circuits are typically fabricated from semiconductor substrates upon and within whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. These electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through conductor layers which are separated by insulator layers.
In addition to the use of transistors as switching elements within integrated circuits, and the use of resistors as electrical circuit load elements within integrated circuits, capacitors are also commonly employed within integrated circuits. Typically, capacitors within integrated circuits are employed as charge storage elements within digital integrated circuits or as passive electrical circuit elements within analog integrated circuits.
A common method for forming capacitors within integrated circuits is to form upon a semiconductor substrate two doped polysilicon layers which are separated by an insulating layer. A capacitor formed through this method is referred to as a planar polysilicon capacitor. A typical planar polysilicon capacitor within an integrated circuit is illustrated within the cross-sectional schematic diagram shown in FIG. 1.
FIG. 1 shows a semiconductor substrate 10 within and upon whose surface is formed a Field OXide (FOX) isolation region 12. The FOX isolation region 12 defines the active semiconductor region of the semiconductor substrate 10. Within the active semiconductor region may be formed transistors, resistors, diodes and other electrical circuit elements. For example, FIG. 1 illustrates a field effect transistor structure formed within the active semiconductor region. The field effect transistor structure comprises a gate electrode 22 which resides upon a gate oxide 20, and a pair of source/drain electrodes 24a and 24b.
Typically, planar polysilicon capacitors within integrated circuits are formed upon the surfaces of FOX isolation regions within those integrated circuits. Thus, within FIG. 1, a conventional planar polysilicon capacitor is illustrated by a first polysilicon layer 14 and a second polysilicon layer 18 separated by an insulating layer 16, all of which layers are formed upon the surface of the FOX isolation region 12.
An unfortunate consequence of forming planar polysilicon capacitors upon the surfaces of FOX isolation regions within integrated circuits is the substantial step height from the top surface of the planar polysilicon capacitor to the top surfaces of the surrounding integrated circuit features formed upon active semiconductor regions. This substantial step height may provide fundamental problems in forming sufficiently thin planarized insulator layers over integrated circuit features adjoining planar polysilicon capacitors formed upon FOX isolation regions. The fundamental problems may limit the ability to form fully functional and reliable integrated circuits. It is thus towards the goal of forming within integrated circuits planar polysilicon capacitors of height comparable to adjoining integrated circuit features within those integrated circuits that the present invention is directed.
The design and fabrication of planar polysilicon capacitors are known in the art. For example, Chi in U.S. Pat. No. 5,173,437 describes a method for forming a double layer planar polysilicon capacitor compatible with sub-micron processing schemes for advanced integrated circuits. The disclosed method provides a planar polysilicon capacitor which is not susceptible to forming polysilicon stringers which deteriorate the electrical performance of planar polysilicon capacitors and the advanced integrated circuits into which those planar polysilicon capacitors are formed.
In addition, a related disclosure from this laboratory, Yang Pan, "Three Dimensional Polysilicon Capacitor for High Density Integrated Circuit Applications," U.S. Pat. No. 5,744,853 , discloses a polysilicon capacitor formed of patterned and inter-leafed polysilicon electrode layers. The disclosed polysilicon capacitor provides the greater levels of areal capacitance needed for advanced integrated circuits.
Desirable in the art is a planar polysilicon capacitor of height similar to surrounding integrated circuit features within integrated circuits within which that planar polysilicon capacitor is formed. Preferably, the planar polysilicon capacitor is formed while simultaneously maintaining the electrical characteristics of that planar polysilicon capacitor.